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Core1553BRT v4.0 Handbook
Using the Verilog QTBENCDEC Module
You can instantiate the QTBENCDEC module in your design and use it to initiate 1553B messages. The
top level of the module is shown below, along with a description of these ports ( Table 6-9 ).
module QTBENCDEC (CLK, RSTN,
BUSPOS, BUSNEG,
TXSTROBE, TXCW, TXDATA,
RXSTROBE, RXSTAT, RXDATA,
BUSY
);
input
input
inout
inout
input
input
input
CLK;
RSTN;
BUSPOS;
BUSNEG;
TXSTROBE;
TXCW;
[15:0] TXDATA;
output RXSTROBE;
output [ 3:0] RXSTAT;
output [15:0] RXDATA;
output BUSY;
Table 6-9 ? Verilog TBENCDEC Port Descriptions
Port
CLK
RSTn
BUSPOS
BUSNEG
TXSTROBE
TXCW
TXDATA
RXSTROBE
RXSTAT
Direction
In
In
Inout
Inout
In
In
In[15:0]
Out
Out[3:0]
Function
16 MHz clock source for the encoder and decoder. All inputs are sampled on
the rising clock edge, and outputs are registered on the rising clock edge.
Active low asynchronous reset; must be pulsed LOW at the start of
simulation.
Connects to the positive side of the 1553B bus.
Connects to the negative side of the 1553B bus.
Pulsed HIGH for a clock cycle to load a 1553B word into the encoder.
0: The encoder transmits a data word.
1: The encoder transmits a command word.
Transmit word
Indicates that the RXSTAT and RXDATA outputs contain valid data.
RXDATA
Out[15:0] Received word
BUSY
Out
Indicates that either the encoder or the decoder is busy; active when transmit
data is queued in the transmit FIFO, or when it is being transmitted.
Table 6-10 ? RXSTAT Value Definitions
Bit
Function
Description
0
Type
0: Data word
1: Command/status word
1
2
3
Burst
Error
From us
Indicates that the data word was contiguous with the previous one.
Indicates that an encoding error was detected in the word.
Indicates that QTBENCDEC transmitted the word.
QTBENCDEC contains a 1553B encoder and decoder. A transmit FIFO is provided, enabling 64 words of
transmit data to be loaded into the module. The maximum 1553B message length that the encoder is
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